OpenLabs handbook

CPU Visual Handbook

Type an instruction, watch the transistors settle.

Two machines, one engine. A generic accumulator microprocessor that spells the instruction cycle out instant by instant, and a single-cycle RV32I datapath that does the whole thing in one. Both modelled down to the transistor. You write the assembly; the model runs it.

Reference model

The machine in the instruction-cycle lab — its registers, its buses, its two instruction formats and its example program — is reconstructed from a lecture deck by Prof. Filippo Valiante Filho, used with his permission. The text here is our own.

Princípio de Funcionamento de um Microprocessador, Prof. Filippo Valiante Filho · prof.valiante.info · what we took, and what we wrote →

Roadmap

The order in which the concepts hold each other up. Not a queue — later phases reach back, and the map shows it.

Your progress0 of 6

Phase 1 · Signals

One wire, one tick

Phase 2 · Gates

Adding, gate by gate

CMOS logic

Phase 3 · Registers and the ALU

Writing a register

Phase 4 · The instruction cycle

One instruction, instant by instant

The generic ISA

Phase 5 · The datapath, all at once

The whole cycle in one tick

RV32I base ISA

Phase 6 · Assembly

Assemble and run your own program

done
where you are
not written yet
The Datasheet · reference, not a step

01 Signals A wire carries one bit, and time is what it takes to settle.
02 Gates Transistors into gates, gates into adders. Nothing is a black box.
03 Registers and the ALU Where a number waits, and where it changes.
04 The instruction cycle Fetch, decode, execute — spelled out as separate instants instead of drawn as one arrow.
05 The datapath, all at once Fetch, decode, execute — as one drawing that actually runs.
06 Assembly Your program is the input. The CPU is the model that consumes it.

Articles and labs

Each phase pairs prose with a model. The article says what is true; the lab is the thing running, and you can break it.

01 Signals

A wire carries one bit, and time is what it takes to settle.

Articles

High or low: what a bit costs ready
Structure of a computer coming
Buses and the clock coming

Labs

One wire, one tick coming

02 Gates

Transistors into gates, gates into adders. Nothing is a black box.

Articles

From transistor to adder ready

Labs

Adding, gate by gate ready

03 Registers and the ALU

Where a number waits, and where it changes.

Articles

The register file coming
The registers a computer cannot do without coming

Labs

Writing a register coming

04 The instruction cycle

Fetch, decode, execute — spelled out as separate instants instead of drawn as one arrow.

Articles

Control is not data coming
Instruction formats coming
The instruction cycle ready
One program, twenty-nine instants coming

Labs

One instruction, instant by instant ready

05 The datapath, all at once

Fetch, decode, execute — as one drawing that actually runs.

Articles

One instruction, end to end coming

Labs

The whole cycle in one tick ready

06 Assembly

Your program is the input. The CPU is the model that consumes it.

Articles

Writing RV32I by hand coming
From total = 10 + 5 + 18 to bits coming
From the generic machine to the 8085 ready

Labs

Assemble and run your own program ready

Handbook assessment

The cumulative assessment has not been authored yet. Available labs and articles remain open for study.