CPU Visual Handbook · lab

The instruction cycle, one instant at a time

A single-cycle datapath settles a whole instruction inside one clock. This one doesn't: fetching the instruction, decoding it, fetching an operand, and writing a result are each their own instant here — a MAR, an MBR and a handful of latches carrying a byte across a single address bus and a single data bus, one transaction at a time. That is the fetch-execute cycle as time instead of as a diagram.

Eight bits, two instruction formats, and a program counter, an instruction register, an accumulator and a temporary — the minimum set a machine needs to run anything at all. LOAD, ADD and STORE are the reference model's own three instructions; LOADM, JMP and JZ are added so a loop can exist.

Step through one micro-step at a time, or let the clock run. The phase shown beside the controls is state the control unit itself holds between ticks — the one thing a single-cycle machine never needs.